1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a MOS semiconductor device of a multilevel interconnection having a LDD (lightly doped drain) structure, and a method for manufacturing the same.
2. Description of Related Art
In a MOS semiconductor integrated circuit, an increase in the memory capacity of a DRAM, a system on silicon, a microminiaturization of transistor cell size, and a multilevel interconnection are advanced ceaselessly. As a result, the microminiaturization and the multilevel interconnection have been surely advanced, however, it becomes more difficult to ensure reliability of circuit elements including transistors. In particular, a threshold of a MOSFET (metal-oxide-semiconductor field effect transistor) having the LDD structure and the multilevel interconnection is greatly influenced by infiltration of moisture from a plurality of interlayer films stacked on a gate electrode of the transistor because it has the multilevel interconnection.
In order to prevent the infiltration of moisture from the interlayer films, a MOSFET semiconductor device of the LDD structure as shown in FIG. 4C has been known. Now, a method for manufacturing this semiconductor device will be described with reference to FIGS. 4A to 4C.
First, a field oxide film 2 for a device isolation is formed on a semiconductor substrate 1 of for example a P-type conductivity by using a LOCOS (local oxidation of silicon) process, and a gate oxide film 3 having a thickness of about 8 nm is formed on the semiconductor substrate 1 excluding the field oxide film 2, by use of a thermal oxidation. Thereafter, boron ions (BF2+) for adjusting the threshold voltage of the transistor, are ion-implanted through the gate oxide film 3 into a device. region of the semiconductor substrate 1 for example with an energy of 35 KeV and a dose of 4xc3x971012/cm2. Furthermore, a polysilicon film having a thickness of about 300 nm is deposited on the gate oxide film 3 by means of a CVD (chemical vapor deposition) process, and a heat treatment is conducted within atmosphere of PH3 or another so as to dope phosphorus into the polysilicon film. The phosphorus-doped polysilicon film is selectively removed by a photolithography to form a gate electrode 4. By using the gate electrode 4 as a mask, for example, phosphorus is ion-implanted with an energy of 20 KeV and a dose of 7xc3x971013/cm2, so that Nxe2x88x92 diffused layers 5 are formed as a source and a drain. Then, a CVD oxide film 6 having a thickness of about 150 nm is deposited on a whole surface of the semiconductor substrate 1 including the gate electrode 4 by means of the CVD process. Thus, it becomes a structure shown in FIG. 4A.
Thereafter, as shown in FIG. 4B, the CVD oxide film 6 deposited on the whole surface of the semiconductor substrate 1 including the gate electrode 4 is anisotropically etched so that the CVD oxide film 6 remains only on a side wall of the gate electrode 4 so as to form a sidewall oxide film 7. By using the gate electrode 4 having the sidewall oxide film 7 as a mask, for example, arsenic is ion-implanted with an energy of 70 KeV and a dose of 3xc3x971015/cm2. Furthermore, a heat treatment is conducted at 900xc2x0 C. for 10 minutes so as to activate ions. Thus, N+ diffused layers 8 are formed as a source lead-out electrode and a drain lead-out electrode. At this time, a principal portion of the LDD structure MOSFET is completed.
Succeedingly, in order to protect the above mentioned LDD structure MOSFET from contamination by various materials formed thereon, as shown in FIG. 4C, a first protecting silicon oxide film 9 having a thickness of about 100 nm is formed on the whole surface of the semiconductor substrate 1 including the gate electrode 4, by an atmospheric pressure CVD process with a raw gas of SiH4 and O2 and a substrate temperature of about 400xc2x0 C. Furthermore, a first protecting silicon nitride film 10 having a thickness of 10 nm to 20 nm is formed on the first protecting oxide film 9 by a thermal CVD process with a raw as of SiH2Cl2 and NH3, a substrate temperature of about 700xc2x0 C. and a gas pressure of about 1 Torr.
Thereafter, a first interlayer BPSG (borophosphosilicate glass) film 11 is formed on the whole surface. For connection to devices including the LDD structure MOSFET, first through-holes (not shown) are formed for connection to the N+ diffused layers as the source lead-out electrode and the drain lead-out electrode, and a first metal layer (not shown) (which can be formed of various metals) is deposited on the first interlayer BPSG film 11 to fill up the through-holes, and then is patterned to form a first level metal interconnection (not shown). Furthermore, a second interlayer film (not shown) is formed on the first level metal interconnection, and second through-holes (not shown) are formed, and a second level metal interconnection (not shown) is formed. These procedures are repeated, so that a multilevel interconnection structure is completed.
In the above mentioned prior art LDD structure MOSFET semiconductor device, variation of the threshold voltage caused by infiltration of moisture is prevented by covering the gate electrode with the first protecting nitride film 10 having a necessary thickness and a sufficient density for shutting out the infiltration of moisture contained for example in the BPSG film 11. Although the infiltration of moisture could be prevented by the first protecting nitride film 10, another problem has newly occurred. Namely, since the first protecting silicon nitride film 10, which has the thickness of 10 nm to 20 nm and covers the gate electrode 4 and which is dense enough to shut out the infiltration of moisture, has a tensile stress of about 1xc3x971010  dynes/cm3, energy levels for trapping electrons and holes are easily formed within the gate oxide film 3 including the neighborhood of the drain and at a boundary between the gate oxide film and the semiconductor substrate 1, with the result that hot carriers accelerated by an electric field in the neighborhood of the drain are trapped in the trapping energy levels, and therefore, the threshold voltage varies.
Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a LDD structure MOSFET semiconductor device having a stable and reliable threshold voltage by preventing infiltration of moisture from interlayer insulator films such as interlayer BPSG films stacked on the gate electrode, and also by minimizing the density of energy levels for trapping electrons and holes, which are formed within the gate oxide film and at the boundary between the gate oxide film and the semiconductor substrate, and a method for manufacturing the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device comprising a semiconductor substrate of a first conductivity type, a first insulator film formed on the semiconductor substrate for confining a device region, a gate insulator film formed on the semiconductor substrate including the first insulator film, a gate electrode formed on the gate insulator film within the device region, a source region and a drain region of a second conductivity type opposite to the first conductivity type, formed in the semiconductor substrate within the device region in self-alignment with the gate electrode, a sidewall insulator film formed on a side wall of the gate electrode, a source lead-out region and a drain lead-out region of the second conductivity type formed in the semiconductor substrate within the device region in self-alignment with the sidewall insulator film and the gate electrode, a protecting insulating film having at least one insulator film and formed on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film, and an interlayer insulator film formed on the whole surface of the semiconductor substrate including the protecting insulating film for isolating the gate electrode from a metal interconnection formed on the interlayer insulator film, the protecting insulating film having the nature of shutting out moisture from an upper interlayer insulator film including at least the interlayer insulator film and of minimizing a stress of the protecting insulating film.
In a first embodiment of the semiconductor device, the protecting insulating film is constituted of a multilayer film composed of a nitride film having the nature of shutting out infiltration of moisture and having a thickness of 10 nm to 20 nm and an oxide film having a compressive stress and having a thickness of 40 nm to 60 nm, which are deposited in the named order on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film.
In a second embodiment of the semiconductor device, the protecting insulating film is constituted of a multilayer film composed of a first oxide film having a thickness of 90 nm to 110 nm, a nitride film having the nature of shutting out infiltration of moisture and having a thickness of 10 nm to 20 nm and a second oxide film having a compressive stress and having a thickness of 40 nm to 60 nm, which are deposited in the named order on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film.
In a third embodiment of the semiconductor device, the protecting insulating film is constituted of a multilayer film composed of a first nitride film having the nature of shutting out infiltration of moisture and having a thickness of 10 nm to 20 nm and a second nitride film having a compressive stress and having a thickness of 30 nm to 100 nm, which are deposited in the named order on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film.
In a fourth embodiment of the semiconductor device, the protecting insulating film is constituted of a multilayer film composed of an oxide film having a thickness of 90 nm to 110 nm, a first nitride film having the nature of shutting out infiltration of moisture and having a thickness of 10 nm to 20 nm and a second nitride film having a compressive stress and having a thickness of 30 nm to 100 nm, which are deposited in the named order on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a first insulator film formed on a semiconductor substrate of a first conductivity type, for confining a device region, forming a gate insulator film on the semiconductor substrate including the first insulator film, forming a gate electrode on the gate insulator film within the device region, forming a source region and a drain region of a second conductivity type opposite to the first conductivity type, in the semiconductor substrate within the device region in self-alignment by using the gate electrode as a mask, forming a sidewall insulator film on a side wall of the gate electrode, forming a source lead-out region and a drain lead-out region of the second conductivity type in the semiconductor substrate within the device region in self-alignment by using the sidewall insulator film and the gate electrode as a mask, forming a protecting insulating film having at least one insulator film, on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film, and forming an interlayer insulator film formed on the whole surface of the semiconductor substrate including the protecting insulating film for isolating the gate electrode from a metal interconnection formed on the interlayer insulator film, wherein the step of forming the protecting insulating film forms a protecting insulator film having the nature of shutting out moisture from an upper interlayer insulator film including at least the interlayer insulator film and of minimizing a stress of the protecting insulating film.
In a first embodiment of the method for manufacturing a semiconductor device, the step of forming the protecting insulating film includes the step of depositing a nitride film having a thickness of 10 nm to 20 nm on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film by a thermal chemical vapor deposition process, and succeedingly depositing an oxide film having a thickness of 40 nm to 60 nm by a plasma chemical vapor deposition process.
In a second embodiment of the method for manufacturing a semiconductor devices the step of forming the protecting insulating film includes the step of depositing a first oxide film having a thickness of 90 nm to 110 nm on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film by an atmospheric pressure chemical vapor deposition process, succeedingly depositing a nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and thereafter, depositing a second oxide film having a thickness of 40 nm to 60 nm by a plasma chemical vapor deposition process.
In a third embodiment of the method for manufacturing a semiconductor device, the step of depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and succeedingly depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.
In a fourth embodiment of the method for manufacturing a semiconductor device, the step of forming the protecting insulating film includes the step of depositing an oxide film having a thickness of 90 nm to 110 nm on the whole surface of the semiconductor substrate including the gate electrode and the sidewall insulator film by an atmospheric pressure chemical vapor deposition process, succeedingly depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and thereafter, depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.
In the above mentioned method for manufacturing a semiconductor device, preferably, the thermal chemical vapor deposition is conducted at a temperature of 700xc2x0 C., the atmospheric pressure chemical vapor deposition process is conducted at a temperature of 400xc2x0 C., and the plasma chemical vapor deposition process is conducted at a temperature range of 250xc2x0 C. to 300xc2x0 C.
In addition, preferably, before the first nitride film having the thickness of 10 nm to 20 nm is deposited by the thermal chemical vapor deposition process, the semiconductor substrate is heat-treated in a deposition machine for depositing the first nitride film, for not less than ten seconds at a temperature of not less than 700xc2x0 C. and a gas pressure of not greater than 10xe2x88x923 Torr.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.